Isn't it great when string_view::substr doesn't get inlined and is 31 bytes? That's -O3 LTO, but callers are cold, which is supposed to be "optimise for size", but is more like "don't inline stuff". There's also pos bound checking, which C++ for some reason requires for substr.

“299 792 458 m/s ought to be enough for anybody” really hasn’t aged well.

Now that CUDA11 is out, some more questions about Ampere are answered. The ISA is the same as Volta and Turing (plus the extensions for new features). At first glance it also looks like there are only minor changes to fixed latencies (and penalties).

I've been catching up on 400Gb/s ethernet phy and the main observation is that 802.3-2018 is a nearly 100MB PDF that still contains things like 2BASE-TL. I'm worried that further evolution is going to be hampered by that fact that no PDF reader will be able to open the spec.

Intel AMX software.intel.com/content/www/us…

I'm generally not very interested in old papers that didn't lead anywhere (so far?) – I'm not a historian. However, I must admit, "A subnanosecond HEMT 1Kb SRAM" is quite an impressive title for a paper published in 1984.

The Dune books have some strong opinions regarding atomic instructions: “Use of atomics [...] shall be cause for planetary obliteration.” Unclear whether this applies to LL/SC as well, but I’m inclined to agree regardless.

It appears that NOP on Cortex-A72 has throughput of 1, which seems rather slow considering that the front end can deliver 3 µops per cycle. On a more positive note, looks like GCC for aarch64 knows that spilling GP registers to the FP ones is an option.

Apparently, there is NUMA node interleaving with cache line granularity. As wrong as it feels, it sort of makes sense if the DRAM throughput is all that matters. The question still remains if it is not a serious design flaw when a single socket needs so much bandwidth.

Pro tip: don't make typos in an inline asm that's inside a loop unrolled 10000 times. It's going to be the assembler that reports the errors. All 10000 of them.

Premature optimisation is the root of all evil.

I really need to take into account how shaky my hands are next time I’m designing a PCB with lots of 0402s that I need to assemble myself. Well, at least I didn’t use any 0201.

.Joe Fitz that paper about dopant based hardware trojans is insane! Thanks for the recommendation! iacr.org/archive/ches20…

(Almost) everything is a matrix multiplication. That includes a few transmission lines and some switches. I've been playing around with 2x2 unitary matrix-complex vector multiplication using 5.8GHz microwave signals. Finally, wrote a post about this. paweldziepak.dev/2021/05/16/mat…

Today, I released uiCA, the "uops.info Code Analyzer". uiCA is based on data from uops.info, combined with a new detailed pipeline model. An online version (that also supports other tools) is available at uica.uops.info (1/3)

SMT solvers are great but it is way too easy to go from a problem that takes a day to solve to a question that won’t be answered before Earth is destroyed by the expanding Sun. Running it under ‘screen’ won’t help with the latter.

Any formal grammar that does not allow trailing commas is ill-formed.

Given: 1. crc32 has throughput 1 on port 1 2. pclmulqdq has throughput 1 on port 5 3. pclmulqdq+pxor can emulate crc32 It seems that fastest crc32 code should divide input in half and issue a crc32 _and_ a pclmulqdq every cycle. Code and numbers at corsix.org/content/fast-c…

Very cool article and I learned multiple new details! Discovering Hard Disk Physical Geometry through Microbenchmarking blog.stuffedcow.net/2019/09/hard-d…

I wrote a few words about an analog distortion effect I built. paweldziepak.dev/2025/06/05/dis…