I published my research on the Apple M1 CPU microarchitectures (Firestorm and Icestorm), with instruction tables describing throughput, latency, and uops for most instructions, and (an insane number of) detailed experiments and measurements. dougallj.github.io/applecpu/fires…

I have added data for Tiger Lake and Zen 3 to uops.info/table.html

New EU-Funding at #SIC: Universität Saarland Professor Jan Reineke has received an Advanced Grant of European Research Council (ERC) for his project 'Abstraction for Safe and Secure Hardware-Software Systems‘ and will now be funded with 2.5 million euros over 5 years. #ERCAdG More: bit.ly/SICERC

On Cascade Lake with a recent microcode update (0x5003102), the loop stream detector (LSD) appears to be disabled. With the older microcode 0x5002f01, the LSD is enabled.

Part 2 of the follow-up to the "Simple Code" lecture is now available. In it, I show how to look through the compiled code using Compiler Explorer, then simulate its scheduling on Intel CPUs using UICA: youtu.be/1tEqsQ55-8I

#Intel released the 76th edition of the Software Developer’s Manuals with fixes, clarifications and #AlderLake intel.com/content/www/us…

nanoBench now has the option to perform cycle-by-cycle measurements, similar to Brandon Falk' Sushi Roll technique (x.com/gamozolabs/sta…) github.com/andreas-abel/n…

The entire #Intel Atom fleet appeared on uops.info site! Congratulations, Andreas Abel!

Good feature of uops.info: "URL" button in the top right corner gets you a URL that preserves the state of the table you've selected (which can be slowish to reconstruct). I was too dim to notice this! Thanks Andreas Abel for pointing this feature out.

Latency, throughput, and port usage data for #Zen4 is now available at uops.info/table.html

Facile: Fast, Accurate, and Interpretable Basic-Block Throughput Prediction arxiv.org/abs/2310.13212 IEEE International Symposium on Workload Characterization (IISWC) 2023 Andreas Abel (Andreas Abel), Shrey Sharma, Jan Reineke