EBADF (@__iameli) 's Twitter Profile
EBADF

@__iameli

Software Engineer stuff. Open Source stuff. Formula one stuff. Lewis Hamilton stuff

ID: 2277375045

linkhttps://github.com/Elijahahianyo calendar_today12-01-2014 18:28:15

3,3K Tweet

310 Followers

910 Following

valigo (@valigo_gg) 's Twitter Profile Photo

I desperately need to learn more math. Recently I invented "lerp" from first principles. Would have saved some time if I knew its industry-standard name :/

Manish Gill (@mgill25) 's Twitter Profile Photo

Found this gem of a comment on HN: "Nobody should listen to anyone who speaks about performance in terms of reasoning about a system instead of profiling it."

kshitij vaze (@vazekshitij) 's Twitter Profile Photo

Except this is not what studying looks like, and I am sick and tired of the internet pretending that it does. Let me tell y'all something. Studying is maddening, okay? It is a pursuit of fanatically trying to understand something that you, for some inexplicable reason cannot

Marc O 🥏🌏🐛🌱 (@cropinvestment) 's Twitter Profile Photo

Hello, Ghana 🇬🇭 Your Excellency, John Dramani Mahama Hello Africa and the world. We 3Farmate are proud to announce the official launch of FAMA—Ghana's FIRST AI-powered autonomous farming robot for large-scale crop production. Founded in 2021 by Clinton 🛸 (CEO) and Koffi-Cobbin

piq and 69 others (@piq9117) 's Twitter Profile Photo

I thought C/C++ or rust was going to be the barrier to entry for hardware then I learned that hardware api is terrible. lol. Spec sheets are different for every manufacturer! fuck that. im just gonna be part of the permanent underclass.

manny🪐 (@willofdaedalus) 's Twitter Profile Photo

yesterday's session was incredible I talked about firmware and we went through a real design challenge for a small problem interfacing with a temperature sensor and logging to an sd card very cool stuff and grateful for the opportunity

Dmitrii Kovanikov (@chshersh) 's Twitter Profile Photo

Python doesn’t care about performance. You’d think it cares about correctness. No. You’d think it cares about static types. Also no. You’d think it cares about tooling. Also no. You’d think it cares about coding practices. Also no. You think it cares about security. Also no.

DevCongress (@devcongress) 's Twitter Profile Photo

Did you enjoy the system design session? Would you like more sessions, perhaps with a longer duration? Additionally, join our Slack channel for more system design sessions.

LaurieWired (@lauriewired) 's Twitter Profile Photo

Modern DRAM is based on a brilliant design from IBM. But, we're still paying for a latency penalty that's existed since the 60s! In this video, I'm introducing my research project (Tailslayer) that immensely reduces p99.99 latency on traditional RAM! By implementing a hedged

Ryan Peterman (@ryanlpeterman) 's Twitter Profile Photo

Leslie Lamport (Turing Award Winner, Inventor of Paxos & Latex): "I would meet with Dijkstra once a week. When he thought of something, had some idea, he would write it down and send it out to people. He sent the first concurrent garbage collection algorithm. I looked at it, and

Ryan Peterman (@ryanlpeterman) 's Twitter Profile Photo

Leslie Lamport (Creator of LaTex): "If you think you know something but don't write it down. You only think you know something. It reveals what you haven't said. And that there's steps in there. You may think they're obvious, but you haven't written them down. And that's where

EBADF (@__iameli) 's Twitter Profile Photo

So basically modern CISC chips are RISC underneath; decoding instructions into μops so the backend can easily parallelize them, but RISC chips mostly map 1:1. Explains why writing ARM assembly always feels verbose

LaurieWired (@lauriewired) 's Twitter Profile Photo

In the 90s, Hitachi came up with a bizarre way to conserve memory bandwidth. Their SuperH architecture, intended to compete with ARM, was a 32-bit architecture that used…16 bit instructions. The benefit was really high code density. If you can fit twice as many instructions

In the 90s, Hitachi came up with a bizarre way to conserve memory bandwidth.

Their SuperH architecture, intended to compete with ARM, was a 32-bit architecture that used…16 bit instructions.

The benefit was really high code density. If you can fit twice as many instructions
ayush.sol🔮👨‍💻🔮 (@ayushagarwal027) 's Twitter Profile Photo

🦀 Rust is finally getting stable tail calls! Folkert de Vries (Trifecta Tech Foundation) just published a great writeup on why this matters and what's happening in 2026. ⚡ Why care? Tail calls unlock stack-safe recursion and blazing-fast state machines, essential for

🦀 Rust is finally getting stable tail calls!

Folkert de Vries (Trifecta Tech Foundation) just published a great writeup on why this matters and what's happening in 2026.

⚡ Why care? Tail calls unlock stack-safe recursion and blazing-fast state machines, essential for
EBADF (@__iameli) 's Twitter Profile Photo

Performance = Instructions per cycle(IPC) x frequency So increasing any of these parameters should result in a performance increase. However, one weird thing is, the IPC is in some ways affected by frequency. Low frequency = longer cycles = more instructions in a cycle