Zip CPU (@zipcpu) 's Twitter Profile
Zip CPU

@zipcpu

FPGA design engineer and blogger, placing particular emphasis on test and formal verification

ID: 822816429313523712

linkhttp://zipcpu.com calendar_today21-01-2017 14:41:38

7,7K Tweet

6,6K Takipçi

142 Takip Edilen

Zip CPU (@zipcpu) 's Twitter Profile Photo
Zip CPU
@zipcpu

20 days ago

Why formally verify a DMA? Consider this, running off the end of memory should generate a DMA error. One DMA passed all of its simulation tests, yet would only generate a memory overflow error under some stall conditions. Were those the ones simulated, or were they missed?