Zip CPU
@zipcpu
FPGA design engineer and blogger, placing particular emphasis on test and formal verification
ID: 822816429313523712
http://zipcpu.com 21-01-2017 14:41:38
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Formally verifying my AXIDMA can take a week or longer of solid CPU time. Today, I fired the proof off using the CVC5 solver. (cvc5 Solver) Other solvers attempting the proof include Z3, Yices2, and Boolector. Let's see which one finishes first.