These nodes don't just pop out of thin air out of nowhere. Bringing things like RibbonFET, PowerVia to market takes literally over a decade of R&D.

So with Arrow Lake (20A) launching by the end of the year, Intel is right at the finish line of 5N4Y.

Yeah. It helps if you can sell your chip at $30k, more than an entire TSMC wafer.

Also note Nvidia is (still) using a 5nm-class node, half a decade old now (mature, depreciated, high-yield). Instead, Intel's idea with PVC was to be the 7nm (I4) *lead* product. Glenn K. Lockwood

Ben Bajarin I’ve asked and so far, no one has sent me that electron microscope image that shows one 3nm transistor.

6/6 - Intel’s proprietary wafer sort capabilities can offer single die sort as well as standard wafer sort. Single die benefit: faster to change temperature vs entire wafer. This is needed as wafer probing is completed at various different temperatures

5/6 - Another interesting thing is this is the first time we have seen Intel publicly reveal package size limits for their various technologies. EMIB can go up to 6x reticle, and they want to achieve >8x reticle by 2028. Foveros today can go up to 4x reticle.

4/6 - Intel believes TSMC was first to market with CoWoS and that’s why it is so dominant. IFS is working to get customers to redesign and requalify their packages for EMIB. See our Accelerator Model for more on IFS packaging wins.
semianalysis.com/p/accelerator-…

3/6 - While presenters were mostly from academia, Intel presented their advanced packaging roadmap. IFS believes EMIB is better than CoWoS in every way with better cost, yield and cycle time and can match even CoWoS-L on performance (we are skeptical).

Pat Gelsinger literally fits in all of these categories. Truly the most underrated tech CEO out there.

Like, give one other company that has ever managed to catch up (never mind regaining leadership) after falling behind on Moore's Law.

seekingalpha.com/article/468758…
Free link: seekingalpha.com/article/468758…

Maynard Handley 🟦 witeken Andreas Schilling 🇺🇦 🇮🇱 What do you mean with 'we dont know the area'?
A14 is 11.8B transistors on 89.75mm² so 131Mtrans/mm²
A17 is 19B transistors on 113.99mm² so 166.68Mtrans/mm²
This is a 1.27x increase

MSI Claw claims up to 150% added performance from new BIOS and GPU driver updates — 28% improvement on average across 19 tested games trib.al/PkoYbum

It seems Panther Lake won’t be another late Q4 product like Meteor and Arrow Lake.

Can someone smarter than me opine about why NVIDIA (*and* everyone else) might still be gluing together reticle-limited chips when Cerebras has gone all-in on monolithic (beyond-reticle) wafer-scale chips?

No, but the magnitude might have. Surely no one was expecting a loss of $7B (on $18B revenue). Else then where were the tweets -before- the webinar.

Intel is on track to regain process leadership next year. Learn more: intel.com/content/www/us…

Here we go Intel Q1 earnings are in.

The quarter performance was better than expected but the drag after hours is the guide came in software on both revenue and EPS.

Highlights for the quarter besides the beat on top and bottom was the strong 31% growth in the company's…