github.com/tangnano20k is a github org to gather info and core development for Tang nano 20k Sipeed

How I remade Another World / Out of This World in hardware on the UP5K #fpga. Thread!⬇️ Detailed write up and full #Silice design release! Includes bitstreams for icebreaker, mch2022, and a bonus board ;) ➡️ github.com/sylefeb/a5k

tangprimer20k (#gowin chip GW2A series) successfully programmed as "PicoRV32 - A Size-Optimized RISC-V CPU". In this video it finds prime numbers correctly!🎇 It means that so far I haven't messed up anything in the new Himbaechel architecture🤪 #apicula #fpga #nextpnr #riscv

The massive Himbaechel-gowin backbone is already in decent condition and works on boards from #tangnano GW1N-1 already out of stock to the last one I have #tangprimer20k😉 It remains for me to implement a large piece of IO. #fpga #apicula #sipeed #gowin

nanoSPC 0.1 for Tang Nano 20k is available. It plays classic Super Nintendo music thru the FPGA. ✅ 32Khz stereo through HDMI. ✅ Up to 99 songs on one microsd. ✅ LED audio level display. ✅ No additional hardware needed other than the nano. Grab it from github.com/nand2mario/nan…

WOOOOO! I know it doesn’t look like much, but this is my fpga testbed. The Arduino is clocking in 8k of data, then requesting encryption, then clocks 8k of data back out and checks it is correct. This is so much faster than the Arduino processor!

New article exploring the internals of the protocols and path used to program the Tang Nano FPGA. From USB (WebUSB) to FTDI (MPSSE) to JTAG and back learn.lushaylabs.com/bitstream-to-f…

Who else is excited for lagless analog output on #AnaloguePocket? Well instead of waiting, you can get it now! Just… don’t worry that it’s only 6 colors… and that those colors are all grey. But hey, it works, with no other hardware but a few resistors

Marcelo Samsoniuk logic destroyer I agree github.com/ZipCPU/eth10g

Excited to release our newest article: Composite Video on the Tang Nano 9K #FPGA - we partnered with Adam Gastineau to dive deep into the NTSC standard. learn.lushaylabs.com/tang-nano-9k-c…

Yay! First launch of BSRAM in ROM mode. Yes, there are flaws, and I’m a lousy artist, but this primitive went through the entire toolkit - from yosys to gowin_pack😆 #fpga #apicula #sipeed #gowin

Yey! The Dual Port BSRAM primitive began to work in #apicula. What is happening: the video memory is a BSRAM with two ports, most of the time the picture is changed by writing to port A, displayed on the screen by reading through port B, but when you press #fpga #sipeed #gowin

Now available: a RISC-V core for the #analoguepocket. This core is designed to expose the Pocket's functionality to software developers, to enable creation of new applications and games utilizing the hardware. I'm excited to see what people will build! github.com/agg23/openfpga…

Yosys 0.36 has just been released and defaults to abc9 on ECP5, iCE40, and Gowin: github.com/YosysHQ/yosys/… In my ECP5 #FPGA experience, the results from ABC version 9 are almost always significantly better. The Yosys manual on Technology Mapping: yosyshq.readthedocs.io/projects/yosys…

New article in an amazing collaboration with Chandler Klüser on the uptrending HUB75 display protocol and how to drive these scalable displays using the Tang Nano 9K #fpga learn.lushaylabs.com/led-panel-hub7…

This is a thread about the CORDIC algorithm, and why it's been living rent-free in my brain for the last couple of weeks 🧵

#RISCV NanoKVM with 3D printed case, coming next week～

Gee! I discovered and corrected many funny features of BSRAM memory, and later this thing started working on #yosys #nextpnr #apicula! This is #Tangnano9k emulating a small system from the 80s with an i8080, 16K ROM, 32K RAM and a serial port.#fpga