Our paper "MasterMind: Many-Accelerator SoC Architecture for Real-Time Brain-Computer Interfaces" has been accepted at ICCD 2021 ! youtu.be/9a5gRrlgHRc

Guy Eichler (Guy Eichler) will present his paper “MasterMind: Many-Accelerator SoC Architecture for Real-Time Brain-Computer Interfaces” at ICCD's Novel Architectures session on Monday 10/25, 12:10–1:10 pm !

Big Milestone for the OSH community: ESP is silicon-proven! Check out the first chip based on the #ESP platform. This work is a collaboration with Harvard and IBM Research, recently published at #ESSCIRC 2022. sld.cs.columbia.edu/pubs/jia_manto… epapers.org/ess2022/ESR/se… ColumbiaCompSci

Join us in Vancouver for a tutorial on ESP at ASPLOS '23! We'll be covering new, exciting features like accelerator design with Catapult HLS, dynamic partial reconfiguration of FPGAs, and an intro to ASIC design with ESP! Early registration deadline is this Friday. ASPLOS

Congrats Guy Eichler on being awarded the Best Presentation at RAGE'23 for the paper "EigenEdge: Real-Time Software Execution at the Edge with RISC-V and Hardware Accelerators" #RAGE23

New: -Edge #RISCV & HW accelerators -RL-guided routing -#memorymapping using DL -CS-RFET -memory disaggregation -#EVcharging - #PCM for analog #inmemorycomputing -non-traditional design of dynamic logic using #FDSOI -SOA in #datacenters semiengineering.com/chip-industrys… #semiconductor

Happening tomorrow at 11 am! Guy Eichler will present his paper "MindCrypt: The Brain as a Random Number Generator for SoC-Based Brain Computer Interfaces" at ICCD'23 in Washington DC

Check out our new #BCI shorturl.at/nKwnH. Subdural, flexible μECoG device features 65,536 channels, with bi-directional wireless communication and power enabling decoding the primate brain with high spatiotemporal resolution. Compare specs to other #BCIs