This has been my favorite website for a few year now: xyproblem.info

Why is it people expect flipping a coin 10 times gives then exactly 5 heads and 5 tails? #Statistics Answer: randcase weight behaviour unexpected stackoverflow.com/a/70875123/275… #SystemVerilog #Statistics daily.jstor.org/statistics-of-…

OMG, if we didn't have enough pictures of cats on the internet...

Q: What is the logic behind the behaviour of reg in #Verilog/#SystemVerilog? A: logic electronics.stackexchange.com/q/606857/38503…

Stop using parent-child when referring to class inheritance in #SystemVerilog #OOP Answer: The parent argument in the uvm_component constructor stackoverflow.com/a/71287147/275…

Are you sure it wasn’t just one day? Now you’re going to miss the AI/ML wave.

#systemverilog #SemiEDA This is how my week is going(almost every other week) Customer: I need 3+3 to equal 7 Me: Can't you add +1 so you have 3+3+1=7 Customer: No, it's legacy code we can't modify. Can't you add a switch to make 3+3==7? Me:🤦

This definitely has been the week of the XY Problem. xyproblem.info. That and #taxes

Pledge to Celebrate Bike to Wherever Day 2022 bikeeastbay.org/civicrm/event/…

went for a 7.0 mile Ride. strava.com/activities/718… #strava #BikeToWorkDay

I'm speaking DVCon India Sep 5th. When is the right time to pay attention to Standards? events.sw.siemens.com/en-US/dvcon-in…

Getting ready to present DVCon India

Panel: Verifying on the Bleeding Edge at Breakneck Speed DVCon India Dennis Brophy

Thanks ⁦DVCon India⁩ !

Here's a perfect example of the XY Problem on the Verification Academy in action tinyurl.com/VA-XY-problem xyproblem.info #verificationengineer #systemverilog #uvm #semiEDA #xyproblem #servingtheNextBug

#dvcon_us starts now with the battle of the #uvm configuration databases #systemverilog

After more than a decade, people still ask "Why #UVM?" verificationacademy.com/forums/uvm/why… #verificationengineer #systemverilog #semiEDA

Pledge to Celebrate Bike to Work Day 2023 bikeeastbay.org/civicrm/event/…

Back at #60DAC presenting 1:30pm today Dragging Debug into a New Era. 60dac.conference-program.com/session/?sess=….

Reminder: DVCon U.S. 2026 Call for Papers – Sept 7th Deadline Approaching! blogs.sw.siemens.com/verificationho… #DVCon #systemverilog #verification #SemiEDA