ALINT-PRO extension added to Visual Studio Marketplace. Benefit from #linting when developing in #VHDL, #Verilog, or #SystemVerilog. marketplace.visualstudio.com/items?itemName… #VisualStudio #VSCode #ALINTPRO #CodeQuality #StaticAnalysis #FPGA

Riviera-PRO 2025.07 Special Release VHDL-2019 64-bit Integer is now available. Benefit from improved precision, resolution, or range when defining physical types and performing arithmetic functions. aldec.com/en/downloads/r… #FPGA #FPGAsimulation #HDLsimulation

Join us on Thursday, January 22 when we review the practical rules, limitations and recommended methodologies for building and verifying mixed-language designs using #VHDL and #Verilog. aldec.com/en/company/eve… #EDA #FPGA #FPGAdesign #FPGAverification #HDL

The 2025.10 release of #RivieraPRO is now available. Performance improvements, system library updates and debugging tool upgrades are among the enhancements. aldec.com/downloads/rivi… #EDA #FPGA #FPGAdesign #FPGAsimulation #OSVVM #UVM #UVVM #VHDL #Verilog #SystemVerilog

Thank you for attending our webinars during 2025, and for asking some questions. If you missed any of the webinars you access recordings from our homepage aldec.com #EDA #FPGA #FPGAdesign #FPGAverification

Do you want to learn some practical rules and recommended methodologies for building and verifying mixed-language designs using #VHDL and #Verilog? If so, join us on Thursday, January 22. aldec.com/en/company/eve… #EDA #FPGA #FPGAdesign #FPGAverification #HDL

ALINT-PRO 2025.12 features a new set of design rules to help users improve correctness, maintainability and IP interoperability within mixed-language designs. Free evaluation version here aldec.com/en/downloads/a… #VHDL #Verilog #SystemVerilog #Linting #CodeQuality

Join us this Thursday (January 22), when we will be presenting some practical rules and recommended methodologies for building and verifying mixed-language designs using #VHDL and #Verilog. aldec.com/en/company/eve… #EDA #FPGA #FPGAdesign #FPGAverification #HDL

Join us on Thursday, February 12, at either 16:00 CET or 11:00 PST, for the fifth installment in our #VHDL2019: Just the New Stuff webinar series, in which we will focus on some of the final pieces of VHDL-2019 capability. aldec.com/en/company/eve… #EDA #FPGA #VHDL

Registration is now open for the Doulos webinar ‘#cocotb - An Introduction for #Python Programmers’, to be held on Friday, February 20. See the agenda and register through our events page here aldec.com/en/company/eve… #PythonProgramming #EDA #FPGA #VHDL #SystemVerilog

#ActiveHDL 17.0 beta release is now available. It is a Windows-based, integrated #FPGAdesign creation and simulation solution for team-based environments. #EDA #FPGAsimulation

Join us on Thursday, February 12 - at 16:00 CET or 11:00 PST - for our ‘VHDL-2019: Just the New Stuff’ webinar. aldec.com/en/company/eve… #EDA #VHDL #VHDL2019

Join us this Friday (February 20) for the Doulos webinar ‘#cocotb - An Introduction for #Python Programmers’. See the agenda and register through our events page here aldec.com/en/company/eve… #PythonProgramming #EDA #FPGA #VHDL #SystemVerilog

Join us on Tuesday, March 17, for the Doulos webinar ‘EDA Playground Live! VHDL Processes, Signals and Drivers’. See the agenda and register through our events page here aldec.com/en/company/eve… #EDA #FPGA #HDL #HDLsimulation

Are you attending FPGA Horizons US East 2026? Join us on Wednesday, April 29 at 14:40 in we present ‘Prevent Late-Stage #FPGA Failures with Advanced #RTL #Linting and CDC Analysis.’ Register here events.american-tradeshow.com/pcbeast26 #EDA #FPGAdesign #DesignRuleChecks

Join us on Thursday, April 23, for a practical overview of design constraints in #FPGAdesigns and learn how they are used in CDC verification. Register and see the agenda here aldec.com/en/company/eve… #EDA #FPGAdesign #FPGAverification #Linting

Our latest tutorial is for our HES-MPF500-M2S150 Ethernet Reference Design, which features Microchip #PolarFireMPF500T and #SmartFusion2 M2S150T devices. Register / sign in to access the tutorial here aldec.com/en/downloads/p… #MicrochipFPGA #MicrochipLibero

Registration is now open for our two-part “Making a Simple #VHDL #Testbench Step-by-Step” webinar series, with part 1 on May 21 and part 2 on June 4. Register here aldec.com/en/company/eve… #EDA #FPGA #FPGAdesign #FPGAverification

Join our ‘Design Constraints for CDC Verification: Bridging Timing, Clocks, and Reliable Synchronization’ webinar on Thursday, April 23. lnkd.in/gBKRZfgf #ALINTPRO #DesignRuleChecks #DesignRuleChecking #FPGAdesign #FPGAdevelopment #FPGAverification #Linting

Riviera-PRO’s Makefile TCL macro can greatly boost compilation efficiency. Check out this tutorial video to see Makefile in action. aldec.com/en/support/res… #EDA #FPGA #FPGAdesign #FPGAdevelopment