VerifSudha (@verifsudha) 's Twitter Profile
VerifSudha

@verifsudha

Helping Scale DV teams

ID: 2560797422

linkhttp://www.verifsudha.com calendar_today11-06-2014 07:18:51

2,2K Tweet

446 Followers

567 Following

VerifSudha (@verifsudha) 's Twitter Profile Photo

Remote work in #verification will has significant impact on sharing the #debug knowledge. How are you bridging this gap? #SemiEDA

VerifSudha (@verifsudha) 's Twitter Profile Photo

Process of narrowing down failures in simulation based debug is chaotic. Streamline debug process by understanding the trails. #verification #systemverilog #debugging

Process of narrowing down failures in simulation based debug is chaotic. Streamline debug process by understanding the trails. #verification #systemverilog #debugging
VerifSudha (@verifsudha) 's Twitter Profile Photo

We often hear 40% of simulation based ASIC #verification project is #debug. But what we don't hear is, why is it so? Here I am letting you out on one of the secret. #SemiEDA

We often hear 40% of simulation based ASIC #verification project is #debug. But what we don't hear is, why is it so? Here I am letting you out on one of the secret. #SemiEDA
Andrew Wygle (@awygle) 's Twitter Profile Photo

Thanks to nMigen's support for custom signal decoders, I can see the exact commands that are flowing to my DDR2 controller at any given time! Stellar work by Catherine on usability as always 😁

Thanks to nMigen's support for custom signal decoders, I can see the exact commands that are flowing to my DDR2 controller at any given time! Stellar work by <a href="/whitequark/">Catherine</a> on usability as always 😁
Edmund Humenberger (@ico_tc) 's Twitter Profile Photo

As a CPU designer, would you want to know about a catastrophic bug in your design you would think would likely never be triggered by real programms with real data?

VerifSudha (@verifsudha) 's Twitter Profile Photo

AXI write transactions just got more interesting! Discover the power of wstrb and the behavior of 1 byte writes in thisdeep-dive into the world of AXI protocols. Unlock the potential of your design and improve your debugging. #AXI #ProtocolMastery youtu.be/m8FnKn9HZFg

VerifSudha (@verifsudha) 's Twitter Profile Photo

Master AXI protocol. Find out what happens when the AXI: AWADDR is fixed to 4KB boundary and length is varied. youtu.be/G5-7td-B-B0 #axi #debugging #verification

VerifSudha (@verifsudha) 's Twitter Profile Photo

It's your first week on the job as new SoC verification engineer at fast paced product company. What's the most important contribution you can do in week 1? #verification