Matteo Rizzo (@_matteorizzo) 's Twitter Profile
Matteo Rizzo

@_matteorizzo

Security engineer at @google, CTF player for @0rganizers and @polygl0ts
Personal account.
Mastodon: @[email protected]

ID: 948881337355767809

calendar_today04-01-2018 11:38:34

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Google VRP (Google Bug Hunters) (@googlevrp) 's Twitter Profile Photo

📢 📢 📢 Calling all vulnerability researchers interested in microcode! Check out our blog post covering EntrySign, the AMD Zen microcode signature validation vulnerability recently discovered by the Google Security team. bughunters.google.com/blog/542484235…

Samuel Tulach (@tulachsam) 's Twitter Profile Photo

Here it is. Didn't have much time to test it out, but the basic functionality should be working. github.com/SamuelTulach/w…

Here it is. Didn't have much time to test it out, but the basic functionality should be working.

github.com/SamuelTulach/w…
Peter Schmidt-Nielsen (@ptrschmdtnlsn) 's Twitter Profile Photo

Should I write an article on the minimal steps to make an FPGA board with some of the most popular parts? For example, here's a summary of the key highlights for making a board using the current gen Xilinx UltraScale+ parts: 1) To put down the FPGA part! 2) Connect the power

Should I write an article on the minimal steps to make an FPGA board with some of the most popular parts? For example, here's a summary of the key highlights for making a board using the current gen Xilinx UltraScale+ parts:

1) To put down the FPGA part!

2) Connect the power