Only 4 days to go: Silexica is excited to co-present with Xilinx at the ISFPGA Conference on Feb 28.Don't miss the chance to learn about how to enhance HLS with Xilinx Vitis Open Source Strategy & Silexica tools. Read our recent announcement & register hubs.ly/H0H7KG10

Touchdown! NASA’s Perseverance rover lands on Mars with Xilinx #FPGAs on board. Learn about our technology used in the mission: bit.ly/3r978va

Xilinx has opened access to the front-end of #Vitis #HLS on @GitHub! Researchers and developers now have the flexibility to extend and customize the front-end of the HLS compilation process using the standard Clang/LLVM infrastructure. Learn more: bit.ly/3uIrbD5

FPGAs are used increasingly as co-processors in data centers. This App Note explains how SLX FPGA accelerates a Fintech design example, leveraging Xilinx’s Vitis Platform’s bottom-up flow, Alveo U200 accelerator card and Vitis quantitative finance library. hubs.ly/H0HJ8w_0

This recently published article by EE Times | Electronic Engineering Times highlights how Xilinx has partnered with Silexica to extend the capabilities of Vitis HLS. The plugin leverages the newly open-sourced front-end of #Vitis #HLS to improve latency and throughput. Read more: hubs.ly/H0JtP0m0

"The news that Xilinx has open-sourced the Vitis HLS front-end is another push to democratize software development for FPGAs." EE Times | Electronic Engineering Times Read the article: bit.ly/2P3U24n #opensource

Join Silexica during Xilinx Adapt: Data Center on March 24-25 from 8 AM to 11 AM (PDT). Visit the partner area and discover how SLX FPGA can accelerate your C/C++ kernel running on an Alveo Accelerator Card! hubs.ly/H0JGrQs0

Thank you to all who attended #XilinxAdapt Data Center last week! In case you missed it, check out the recording of Stephane Gauthier´s presentation, "Maximize C/C++ Kernel Performance in Alveo accelerator cards using SLX FPGA" here. hubs.ly/H0Kf0g10 #FPGA #HLS #Xilinx

Miss #XilinxAdapt: Data Center? We’ve got you covered! Watch our event on-demand now and catch up on the latest #datacenter innovations from Xilinx and our partners. View now: xlnx.com/3syjUnO #ai #cloud #database #enterprise #hpc #livevideo #smartnic #storage

The recently published article by Markt&Technik highlights how the SLX Plugin extends the capabilities of Xilinx Vitis HLS. The plugin leverages the open-sourced front-end of #Vitis #HLS to improve latency and throughput. Read now (German content only) hubs.ly/H0Kz3gT0

AI applications contribute to the use of FPGAs as co-processors in data centers. Our App Note shows how SLX FPGA accelerates an AI-related face detection design example, leveraging the bottom-up flow of Xilinx Vitis 2020.2 & Alveo U280 accelerator card hubs.ly/H0KShnk0

Connect with Silexica at Enyx On-Air: Spring 2021 next Tuesday, April 20 from 09:00 AM to 12:00 PM (ET). Luis G. Murillo will participate on the keynote panel to discuss challenges using #FPGA for trading and what you need to know to succeed. Register now: hubs.ly/H0L1_1W0

Learn more about how to identify #FPGA hotspots within your application with fast and accurate high-level latency estimates using SLX FPGA here: hubs.ly/H0LHHkp0 #HowTo #HLS #SLX

Pragmas and directives are fundamental to #HLS design methodology, but getting to the correct pragmas can be complex and time-consuming. Our blog post shows how SLX FPGA quickly guides you to the best implementation for your application! Read here. hubs.ly/H0M1dw20

Thanks for joining Enyx | now part of Exegy On-Air webinar! It was a pleasure to discuss the "Challenges with using #FPGA for trading & what you need to know to succeed?" in the keynote panel and to present SLX FPGA! In case you missed it, check out our presentation: hubs.la/H0MMsFy0

The age of acceleration is upon us, and as #embedded technology evolves and takes a new shape, it is important to ease the transition from one program to another. Learn how SLX #FPGA helps creating a new relationship between #SW & #HW engineers. hubs.la/H0N3D8D0

How to implement radar-based adaptive beamforming algorithms using #HLS? Read how SLX FPGA achieves lower latency and cuts development time from weeks down to minutes compared to hand-optimization for similar cost of resources: hubs.la/H0NyCDZ0 #FPGA #embedded

In our latest How to video, learn how to find and remove loop carried dependencies within your application with fast and accurate latency estimates using SLX FPGA. Watch#Ho the full video here: hubs.la/H0Pl95g0 #FPGA #SLX #HowTo

Next week, Silexica will join the #FPGA Conference Europe 2021 to talk about high-level design and the future of HLS! Learn more about how SLX FPGA and Silexica's future as part of the Xilinx family can democratize adaptive computing. Register now hubs.la/H0Rp2kS0