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CEASER (MICRO18) is a promising mitigation for cache timing attacks. But the use of a crude cipher nullifies its usefulness. Shows that it ain't easy to design processors for security and get both right Read more in BRUTUS: ieeexplore.ieee.org/document/89500… Rahul Boddhuna Patanjali @VinodG93

Check out the paper on hardening encryption used as a security measure to prevent cache timing attacks. Well done Rahul Boddhuna @VinodG93 Patanjali !

Prof. V. Kamakoti, IIT Madras CSE Dept. has been bestowed with 'Abdul Kalam Technology Innovation National Fellowship' for his work ‘Design of SHAKTI Based Secure Microprocessor’. Heartiest congratulations to him! #ShaktiProcessor #Technology #Innovation DSTIndia @PIBHRD The Students Circle ➐

Among all the reasons to remember 2020, we'd remember it for a virtual birthday celebration. Wishing our beloved Chester Rebeiro sir a very happy birthday!🎂 Special thanks to the organisers Milind Srivastava , Nikhilesh Singh and Prithwish.