Am I losing my gd mind or does this reset portion of my code look like Eugene Krabs' daughter Pearl

Development is well underway thanks to Cyo coming on board. Cast your vote!

Back on my bs

The next year in retro is about to be wild.

Come hang! Will be a good time.

An absolute madman and pioneer. If anyone can do it, you can Red!

First round of interviews for a senior FPGA engineer position in an hour. The nervous excitement is real! 🥴

Interview went well! It was just myself and an embedded engineer... The CTO couldn't make it due to something coming up. Slightly disappointing but hey, I get high priority stuff comes up for C-levels. Until the next interview, back to work on the next firmware update for 64HD!

Holy crap, the company I interviewed with today already setup a second interview for tomorrow at the same to for the CTO and myself to talk. I'll just assume the quick interview succession means that the first interview went well! 😄

Once these boards are in my hands and assembled, the FPGA majik can begin...

This will be a really fun stream, highly recommend tuning in. zombiphoenix.bsky.social are awesome alone but add @gravebook into the mix? It'll be a whirlwind.

Second interview for Senior FPGA role : ✅ I feel like I just went on a date and now I'm like "I wonder when they will text me, we would make a great couple!" 😂

Haha tmds go brrrrrrrrrr

The fire memes from Mike keep coming haha infoframes go brrrrrrrrrrrrr

ITS HAPPENING! Im getting flown on Sunday out to be on site for the last round of interviews for the Senior FPGA role! Granted, there will be 4 consecutive interviews when I am on site. But if the visit/interviews go well... Then I get the job. HYPE!

Back down into the FIR filter rabbit hole I go... Mapping 2D filter data and coefficients into a 1D FIR filter. How deep does the rabbit hole go, Alice?

Reminder to engineers who code regularly: If your design seems too complicated, it probably is. Simplify simplify simplify!