#ICYMI We are working together with Microsoft on the design verification of #CHERIoT #Ibex to bring class-leading hardware memory safety to applications with tight power, area and financial budgets. Discover more about the collaboration: lowrisc.org/news/lowrisc-a…

Interested in #Sonata? Our Hardware Digital Design Lead, Gregory Chadwick, broke it down at a RISC-V demo session. Watch now to discover the latest on #CHERIoT, the Sunburst Project & a live demo on using CHERI memory safety features on the Sonata board: youtube.com/watch?v=kCeDO7…

Find out why our CEO, Gavin Ferris, believes a Golden Age of open source silicon is on the horizon! Catch Gavin's full interview with RISC-V's CEO, Calista Redmond, about lowRISC's work, the #OpenTitan project and the future of #opensource silicon here: youtube.com/watch?v=SS8eCJ…

Whether you need help developing or integrating open #silicon IP, or would like support or training for your #OpenTitan or #Ibex based design, lowRISC is here to assist! Reach out to our team via [email protected]!

Get started with #CHERI today! You can find software, build flows and examples for a full micro-controller system utilizing the #CHERIoT Ibex core on lowRISC's #Sonata project GitHub! Explore our repository now: github.com/lowrisc

The Sunburst team is pleased to announce the availability of Sonata / CHERIoT boards via international distributor Mouser Electronics: mouser.com/ProductDetail/…

All systems contain a RoT, it’s the part that you assume ‘always works’ even when under attack. But what's the difference between a software and silicon RoT? Gavin Ferris explains the concept of a silicon RoT and its importance in #hardware #security: lowrisc.org/news/safetydet…

#OpenTitan offers commercial-grade security in a transparent, verified and flexible design. Recently, Gavin Ferris described how the world’s most active #opensource silicon project delivered the world's first commercial-grade open #silicon: youtube.com/watch?v=Z3THgx…

In the challenging world of embedded systems, the #Sonata board provides an efficient route for developers to explore & leverage the #security benefits of #CHERI. Learn more about how Sonata affordably offers streamlined debugging, configurability & more: lowrisc.org/news/unveiling…

Apply now for the Digital Security by Design (DSbD) Access Programme! Get access to our Sonata FPGA board, expert technical support to experiment with cutting-edge cyber security technology + a possible £15,000 in funding! digicat.org.uk/3X5OwPf

#CHERI could prevent ~70% of current exploits w/o requiring legacy software to be completely re-coded, yet to date it's been out of reach for many critical applications where power, memory & cost are at a premium. Discover how CHERIoT-Ibex addresses this: lowrisc.org/news/lowrisc-a…

📢We're excited to collaborate with Digital Catapult on the DSbD programme, offering UK tech companies access to our game changing FPGA Sonata board. Explore #CHERI security enhancements to strengthen product resilience & reduce vulnerabilities. Apply here:digicat.org.uk/3X5OwPf

5 yrs ago, with our partners, we began working to bring to market the world’s 1st commercially viable, collaborative, #opensource silicon RoT design, while using the project as the proving ground for the #SiliconCommons. Discover how via EE Times | Electronic Engineering Times: eetimes.com/ushering-in-a-…

On the RISC-V blog, Microsoft explains how #riscv extended with #CHERI technology can prevent a wide range of exploits & vulnerabilities in microcontrollers. We're excited to see our work with UK Research and Innovation on the Sunburst Project highlighted ➡️ riscv.org/blog/2024/08/c…

Interested in joining RISC-V Taipei Day? Mark Hayter, Chief Strategy Officer & Co-Founder of our OpenTitan partner Rivos Inc., will be sharing the transformative benefits of leveraging the #riscv ecosystem to build SoCs for #AI applications. Register🔗 twiota.org/RISC-V/Reshape…

Explore how tech clusters drive collaboration to fuel innovation in the #defence and security ecosystem at CyNam's East of England event. A panel, featuring our CEO, will be discussing best practices and strategies for shaping the UK’s horizons 🔗 eventbrite.co.uk/e/exploring-te…

As part of the Digital Security by Design (DSbD) Access Programme companies will get the chance to work with our innovative #Sonata FPGA board! Interested in what the board can do? Watch Greg Chadwick's demo of #CHERI memory safety features using it: youtube.com/watch?v=kCeDO7…

Tomorrow at RISC-V Taipei Day, catch Mark Hayter, Chief Strategy Officer & Co-Founder of our partner Rivos Inc. as he shares how combining open, commercial & custom #RISCV cores helps deliver their optimized high performance solution for #AI workloads. 🖥️ twiota.org/RISC-V/Reshape…

In today's talk at RISC-V Taipei Day, Mark Hayter highlighted how combining open, commercial & custom #RISCV cores helps deliver their optimized high performance solution for #AI workloads.

We're proud to partner with Digital Catapult on the Digital Security by Design (DSbD) Access Programme, an initiative that will provide a real-world test platform for UK-based companies to experiment with CHERI technology using our innovative #Sonata FPGA board. Apply today➡️ lowrisc.org/news/apply-now…