sergey (@sergeykhbr) 's Twitter Profile
sergey

@sergeykhbr

Developer. Can take a screenshot of your blue screen.

ID: 429199627

linkhttps://github.com/sergeykhbr/riscv_vhdl calendar_today05-12-2011 17:46:18

211 Tweet

8 Takipçi

148 Takip Edilen

Massimo (@rainmaker1973) 's Twitter Profile Photo

A coffee table with printed cast-in hexagon panels that can be individually illuminated [read more: buff.ly/42OhZxr] [video: buff.ly/3pPAao1]

Santiago Víquez (@santiviquez) 's Twitter Profile Photo

If you are having a hard time visualizing all the layers and matrix operations inside an LLM, then you'll love this website! Check it out: bbycroft.net/llm

sergey (@sergeykhbr) 's Twitter Profile Photo

I would like to share my setup. Mounted KC705 and Inspur FPGA boards. Two FPGAs are better than one. Especially when they share a PCIe slot like good little accelerators. Sharing is caring. #AI #FPGA

I would like to share my setup. Mounted KC705 and Inspur FPGA boards. Two FPGAs are better than one. Especially when they share a PCIe slot like good little accelerators. Sharing is caring. #AI #FPGA
sergey (@sergeykhbr) 's Twitter Profile Photo

Enabling the second 32-bits BAR, 1GB size on FPGA leads to disabling all nvme disks, so that even BIOS cannot see them. Awesome behavior

sergey (@sergeykhbr) 's Twitter Profile Photo

HDMI from FPGA - it's alive. Test pattern finally shows up, though the colors look like a shader went off-script. TMDS lanes, sync, and timing are solid. See github.com/sergeykhbr/gpu… — next step: fixing chroma confusion. #FPGA #HDMI #Verilog #gpu3d #HardwareDev

HDMI from FPGA - it's alive.
Test pattern finally shows up, though the colors look like a shader went off-script.
TMDS lanes, sync, and timing are solid.
See github.com/sergeykhbr/gpu… — next step: fixing chroma confusion.
#FPGA #HDMI #Verilog #gpu3d #HardwareDev
sergey (@sergeykhbr) 's Twitter Profile Photo

Limitations, limitations… it's starting to feel like most implementations aim less for full spec compliance and more for the bare-minimum 'demo-friendly' subset that's easy to market.

sergey (@sergeykhbr) 's Twitter Profile Photo

I decided to get another FPGA, this time with passive cooling - the previous one was way too loud for a home lab. The new one, a Gidel HawkEye-20G-48, is perfect. Gidel has been great and already shared the pinout with me.