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#ICYMI: RISC-V leaders, pioneers, and researchers are dedicated to RISC-V development. Check out some of the momentum we’ve heard during today’s incredible round of technical sessions, invited talks, and more: “Developers need fast and easy access to real hardware to build and

Let’s keep the momentum going at #RISCVSummitEurope! ⭐ Day 3 is packed with insights and innovation, including: 9 a.m. | Dive into the state of open source chip design in Europe and discover how RISC-V is powering progress across the region. 2:45 p.m. | Don’t miss the

“RISC-V in space is becoming a tangible reality, with several missions already flying it.” 🌌 The future of space computing is here! Join @ESA’s Lucana Santos at 11:30 a.m. in Gaston Berger (S2) to explore the growing role of RISC-V in space missions and RISC-V-based innovations

Dive into the significance of the RVA23 profile in advancing the RISC-V ecosystem. Join Mark Hayter, Chief Strategy Office and Co-Founder of Rivos, at 2:30 p.m. in Gaston Berger (S2) to explore how the RVA23 drives software portability and expands RISC-V adoption across servers,

Let’s gather for a heartfelt “see you later” and celebrate all we’ve accomplished together. Join us at 5 p.m. as BSC-CNS’ Teresa Cervero brings this incredible week to a close. Thank you to all our attendees for making this week such a success! And, a special shout-out to all

High Performance Computing (HPC) unlocks the ability to simulate complex, real-world problems, as well as power AI and ML workloads. As increasing user demand for more capability meets a growing focus on sustainability, RISC-V offers a flexible and efficient alternative to

We had a great week in #Paris at the RISC-V International. Very productive talks with PULP Platform and nice exchange with Axelera AI about extensions for wireless communication. #Satellites and #submarines were also part of this week European Space Agency NASA Many thanks to Research in Germany - Initiative of the BMBF #France #risc

Today marks 15 years since #RISCV was created by SiFive’s co-founders. Today RISC-V is in billions of devices and SiFive would like to thank all who have contributed to the remarkable growth and progress of RISC-V over the years. #MyRISCVJourney 🔗 sifive.com/blog/from-berk…

🚀 MEDIATE joined RISC-V International Summit 2025 in Paris to present “HW-extended Containers on FPGA-based RISC-V SoC” — enabling reconfigurable RISC-V subsystems for secure, flexible Edge–Cloud systems. Great tech & great exchanges! 🔗 mediate-horizon.eu/mediate-at-the… #CyberSecurity #MEDIATE

Happy 15th Birthday, RISC-V! Fifteen years since Krste Asanovic, Yunsup Lee, Andrew Waterman, and David Patterson at UC Berkeley finally agreed to create a new instruction architecture (ISA), RISC-V has become the world’s 3rd largest, powering everything from edge AI to

Another incredible RISC-V Summit Europe is in the books! A huge thank you to everyone who made last week’s #RISCVSummitEurope a success, from our attendees and sponsors to the brilliant developers and innovators driving RISC-V forward. Catch up on some of the latest news and

At the recent #RISCVSummitEurope, DeepComputing showcased the new DC-ROMA RISC-V AI PC. 💻 Built for developers pioneering edge and AI-native applications, it delivers local AI compute, enabling complex AI models such as LLMs to run entirely on-device, without relying on the

.BrainChip is now integrating Andes Technology’s RISC-V cores with its NPUs. Andes’ QiLai SoC and Voyager development board, combined with BrainChip’s Akida AKD1500, streamlines the development process for advanced RISC-V applications. 🔗 hubs.la/Q03nf6cx0

What started 15 years ago at UC Berkeley has become a global force for innovation, and companies like Lauterbach have been there from the start. In this latest blog, Lauterbach reflects on its journey alongside RISC-V: from key contributions to the RISC-V Debug Spec, E-Trace,

Remember when "big data" was the buzzword? Today, every device, no matter how small, generates mountains of data. The real question now is: how do we process it intelligently and efficiently, whether we’re in the cloud or on the edge? 🔎 Enter Cervell™, Semidynamics'

🎉 Still buzzing from the energy at #RISCVSummitEurope last week? You’re in luck. Registration is now OPEN for RISC-V Summit North America! Register today for the chance to see how RISC-V is defining the future of open computing in Santa Clara, CA this October:

🚨 .Red Hat and SiFive are partnering to bring Red Hat Enterprise Linux support to the growing RISC-V community. Red Hat Enterprise Linux 10 is available in developer preview on the SiFive HiFive Premier™ P550 platform. This collaboration enables developers to create,

“Ultimately, the rise of RISC-V in European automotive is not merely a technical transition but a strategic play for innovation, resilience, and technological sovereignty.” Pablo Valerio of EE Times | Electronic Engineering Times highlighted how RISC-V is rising as a critical technology in automotive thanks

From EVs to autonomous driving, software is redefining the automotive industry. As cars evolve into intelligent, connected platforms, RISC-V delivers the open, flexible compute needed to drive innovation forward. 🔍 Explore how RISC-V is enabling next-gen automotive AI in the

🎥 From member keynotes to insightful panel sessions with RISC-V leaders and pioneers, all #RISCVSummitEurope sessions are now available on RISC-V International’s YouTube channel! Missed a few? Now’s your chance to catch up: hubs.la/Q03pM2bn0 📷 Event photos are also live