Customized Parallel Computing research group
@customparcomp
OpenASIP 1.23 released! It's mainly a maintenance release that adds LLVM 12 support and removes support for older than LLVM 11 to clean up the code base. openasip.org/download.html Thanks FitOptiVis CPSOSAWARE EU funded project @sochubfi for supporting the Customized Parallel Computing research group group's work!
A presentation about our ongoing work on PoCL-R: Distributed OpenCL Runtime for Low Latency Offloading available: youtu.be/Usj0CPC8zEs PoCL developers OpenCL API FitOptiVis CPSOSAWARE EU funded project
OpenASIP 1.24 released! Adds LLVM 13 and first steps for Blocks CGRA support. openasip.org/download.html Thanks FitOptiVis CPSOSAWARE EU funded project @sochubfi for supporting the Customized Parallel Computing research group group's contributions!
Emerging memory technologies could enable extremely energy-efficient compute devices in the future. Read how domain wall memories can be utilized efficiently with our SHRIMP method. ieeexplore.ieee.org/abstract/docum… @TampereUni Customized Parallel Computing research group cfaed | TU Dresden 🇪🇺 FitOptiVis CPSOSAWARE EU funded project
OpenASIP 1.25 is now out. It supports LLVM 14 and adds partial retargetable inline asm support and loop buffer compilation features. openasip.org/download.html Thanks to CPSOSAWARE EU funded project for supporting the Customized Parallel Computing research group group's contributions! @sochubfi llvm.org
The open-standard RISC-V ISA has made the open source hardware community more active but there has been a lack of tools for customized RISC-V processors. Read how we added support for RISC-V based ASIPs to the upcoming 2.0 release of the OpenASIP toolset. researchgate.net/publication/36…
VLIW processors exploit ILP efficiently but suffer from bad code density in serial parts where instruction packets cannot be fully utilized. Read how we increased flexibility and energy efficiency by using both a TTA and RISC-V based ISA in one processor. researchgate.net/publication/36…
OpenASIP 2.0 is out! It has the first #RISCV customization features, improved FU generation, LLVM 15, IP wrapping, among other new features! @sochubfi CPSOSAWARE EU funded project @openhwgroup openasip.org/release_2_0.ht…
Check a demo made with some of our final technical outcomes from the CPSOSAWARE EU funded project EU project: Nano-PoCL, PoCL-R and AlmaIF v2. Offloading OpenVX from a nanodrone to an FPGA using OpenCL as the offload API. Exciting stuff! youtu.be/GtNsznRk5jE OpenCL API PoCL developers
HW accelerators require vendor-specific steps to use. A generic memory-mapped interface helps integrating them to a diverse OpenCL platform. Our interfacing work is now published in doi.org/10.1016/j.micp… and the code available in the PoCL developers repo! OpenCL API CPSOSAWARE EU funded project
Our article introduces a dual-mode processor that utilizes ILP statically when available, without suffering from low code density when it's lacking. The architecture, supported by a novel compilation method, enables fine-grained mode switching. Read more: ieeexplore.ieee.org/document/10330…
As part of @sochubfi, CPC successfully taped out a customized TTA-based Digital Signal Processor (DSP). "Beaivi DSP" was fully designed and C-programmed by using the OpenASIP tools developed by the group since the 2000s: tuni.fi/cpc/headsail_t… Informaatioteknologian ja viestinnän tiedekunta