DDR3 matching under +-1mm

Complete redesign RF layout and power circuit for AD9361. No external RF circuit yet, will put on MEMS switch network for multichip phase syncing.

32bit bus with 2mm matching, hard to balance group center length vs matching variant, especially in a short part distance and only through hole vias. Hope it works.

I guess it can be done before friday...

I doubt if anything wrong with my schematic, as well as when I doubt if it could be routed by capturing the schematic. my context is too small for this job.

next level of open source hardware sdr you want to have based on:

Jerry Giant and ALPHA OL-107E paste i only buy 30g at a time, these things easily go bad when storing out of the fridge

Remake of a HackRF AFE. CPLD from xilinx is expensive and hard to source, would you go with an ice40up5k? or a chinese clone of that CPLD?

shut up and take my money!

A life i wanted, but i spent some 20 years on a chiar instead on a saddle. Do you ever weight the importance of book intelligence over physical in your life? youtu.be/N-01vbIM8TU?si…

Call it a day.

Everything m.2, starlink direct to cell.

Can it be m.2'd ?