Victor Suarez Rovere (@suarezvictor) 's Twitter Profile
Victor Suarez Rovere

@suarezvictor

Software, Electronics, DSP. Ready for consulting work.
[email protected] / @[email protected]

ID: 146132212

linkhttps://github.com/suarezvictor calendar_today20-05-2010 17:33:24

3,3K Tweet

1,1K Followers

801 Following

Frans Skarman (thezoq2@mastodon.social) (@thezoq2) 's Twitter Profile Photo

I now have a Spade playground at play.spade-lang.org. It compiles the Spade code and simulates it using Verilator right in the browser thanks to WebAssembly

Victor Suarez Rovere (@suarezvictor) 's Twitter Profile Photo

With this new tool, you can finally know the REAL capabilities of JLCPCB, like for example, drill hole to pad is 0.18mm (unlike what's stated on their crappy page)

With this new tool, you can finally know the REAL capabilities of JLCPCB, like for example, drill hole to pad is 0.18mm (unlike what's stated on their crappy page)
Jan Gray (@jangray) 's Twitter Profile Photo

This work tops SERV for most *harts* per FPGA and rivals GRVI Phalanx for peak MIPS per FPGA. BRISKI employs HW multithreading well to achieve high Fmax, latency tolerance, and a clean frugal datapath. Riadh will soon present the kilocore SoC architecture at FPGA Europe (IIRC).

This work tops SERV for most *harts* per FPGA and rivals GRVI Phalanx for peak MIPS per FPGA. BRISKI employs HW multithreading well to achieve high Fmax, latency tolerance, and a clean frugal datapath.

Riadh will soon present the kilocore SoC architecture at FPGA Europe (IIRC).
Sam M (@samerps) 's Twitter Profile Photo

New update on combining FastHenry and Blender ๐Ÿ”ถ , I've added the ability to calculate the mutual inductance between objects! Also developed a basic UI inside Blender to visualise the results and to highlight the inductively coupled objects. This video shows some examples of what

nand2mario (@nand2mario) 's Twitter Profile Photo

Starting to port this MiSTer core. Getting the CPU to build is ok. However 32-bit machines won't be easy. For one, the core relies on high Fmax (100Mhz). A quick build gets only 70Mhz. Also it seems Gowin5 has weaker DSP w/o ALU54, making the ALU slower. We'll see how this goes.

Starting to port this MiSTer core. Getting the CPU to build is ok. However 32-bit machines won't be easy. For one, the core relies on high Fmax (100Mhz). A quick build gets only 70Mhz. Also it seems Gowin5 has weaker DSP w/o ALU54, making the ALU slower. We'll see how this goes.
Computaciรณn, Exactas - UBA (@computacionuba) 's Twitter Profile Photo

El diario @Pagina12 entrevistรณ al profesor e investigador Diego Garbervetsky, quien brindรณ un anรกlisis detallado sobre el mayor fallo informรกtico de la historia. Nota de Pablo Esteban. pagina12.com.ar/753698-el-mayoโ€ฆ

Luke Wren @wren6991@types.pl (@wren6991) 's Twitter Profile Photo

I just published the v1.0 release of Hazard3, my 3-stage RISC-V core. There aren't many new features, but there's a lot of cleanup and maintenance work that will make it a better platform for development going forward. Read the release notes here: github.com/Wren6991/Hazarโ€ฆ

Luke Wren @wren6991@types.pl (@wren6991) 's Twitter Profile Photo

Someone is already running RISC-V NOMMU Linux on RP2350. Knew I was going to get sniped on that one. github.com/Mr-Bossman/pi-โ€ฆ

Enjoy Digital (@enjoy_digital) 's Twitter Profile Photo

The LiteX-M2SDR is now available in our shop! enjoy-digital-shop.myshopify.com - Artix7 XC7A200T FPGA. - AD9361 RF transceiver. - SI5351 Clocking. - PCIe Gen2 X4 interface. With fully open-source LiteX/LitePCIe based gateware and software available here: github.com/enjoy-digital/โ€ฆ