While at home enjoy one of the flagship conferences on solid-state circuits. Sunday March 22 will kick off CICC 2020. First IEEE SSC Society fully-online conference. Keynotes will be free to attend ieee-cicc.org/virtual-event-…

Jointly with SiFive, we presented Tucan last week at CICC. Please ask questions or add critics. We'd like to get feedback for next chips slides at docs.google.com/presentation/d…

Bus protocols to allow direct communication among masters and slaves in low-energy applications. Compared to AHB-Lite/APB, a 5X clock cycle reduction when sending data from a peripheral module to another module at the system bus ieeexplore.ieee.org/document/90506…

If you like integrated circuits, here is the NetFlix of IC design (free for a limited time):

“Here’s a pic of kitting up the final components. QC data came out beautiful. Really excited for the Yale University data - huge kudos to the team.” At-Home #COVID19 #test. Yale will validate against laboratory standard. Scaling in parallel to empower everyone #Coronavirus Gates Foundation

Molbio expert & #internship. Inspired by design of our at-home #coronavirus #test. Come Help. Guilford CT or my lab. In validation now Yale University, scaling in parallel. World needs early #virus detection. [email protected] or DM. #DIYBio #biohacking #python #DNA #SARSCoV2

Detecting bugs and spec absences --> Simulation and Formal: The Best of Both Domains for Instruction Set Verification of RISC-V Based Processors. We'd appreciate any feedback: onchip.uis.edu.co/pdfs/fs_p.pdf Thanks Symbiotic EDA Zip CPU for formal training

Love to see this: arm.com/-/media/global… For several reasons. Two of them: 1. Great data on Arm model to build up an SoC. Hiden before after NDA. 2. RISC-V pushing is working since Arm is pushing back. Great for everyone. Arm has great products! IP just for TSMC 22nmULL.

On building USB3+ and PCIe4 interfaces for low-cost tech nodes, the CDR is a hefty block to get it right. Jitter noise requires "massaging" to have a proper CDR response. Check our digital CDR and techniques to achieve stringent jitter specs: ieeexplore.ieee.org/document/89103…

If you need a fast DAC, in terms of implementation and performance, for your testing activities, check this trick out: All-Digital FPGA-based DAC with None or Few External Components. BTW, you can do it with an MCU or similar hackaday arxiv.org/pdf/2008.00572…

I put together a history of SiFive for a CICC talk earlier this year, and now the video is up: youtube.com/watch?v=CmGIJM… #riscv

An excellent article on the role of point of care ultrasound during the COVID-19 crisis.

NVRAM license macros for std CMOS are quite expensive. We have managed to get a small-macro-first-approach silicon-proven NVRAM cell. We even proved an NVRAM PUF concept with it. Presented at IEEE ISCAS #iscas2020: ieeexplore.ieee.org/document/91804…

Tim Edwards from opencircuitdesign.com and efabless.com made a great summary of why chip design still quite closed-sourced youtu.be/nY6FVsAvrUo He also introduces a lot of work done in order to get skywater-google endeavor works. hackaday.io/project/152709…

@[email protected] Goran_Mahovlic My first working silicon designed and verified exclusively with open source tools.

A drug that is commonly used to treat tapeworm infections might help to prevent the formation of atypical fused cells in the lungs of patients with COVID-19, according to a paper published in Nature. go.nature.com/31RsJgX

Watch Starship's fourth flight test x.com/i/broadcasts/1…

Dynamicland's new documentation space will go online on Sept 4. As a prelude, here is a video about Dynamicland's precursor. youtube.com/watch?v=uI7J3I…