I've been studying Frank van den Hoef’s VERA Versatile Embedded Retro Adapter, used by the Commander X16 project, and wrote a post about it: epsilon537.github.io/boxlambda/unde… #VERA #Retrocomputing #FPGA #CommanderX16 #BoxLambda

I integrated the VERA Versatile Embedded Retro Adapter into the BoxLambda SoC. epsilon537.github.io/boxlambda/inte… #FPGA #RISCV #Retrocomputing #BoxLambda #VERA

I added an SD Card Controller and File System to BoxLambda: epsilon537.github.io/boxlambda/sd-a… #FPGA #RetroComputing #ZipCPU #BoxLambda

Here's a short Blog post about Post-Implementation Memory Updates on BoxLambda (Arty-A7): epsilon537.github.io/boxlambda/post…

I added a Dual YM2149 core to BoxLambda: epsilon537.github.io/boxlambda/dual… Here's a short demo: youtu.be/whIKsVm54Ko Chiptunes. Yay!

A new post on the BoxLambda Devlog: An attempt at a PicoRV32-based Soft DMA Controller. epsilon537.github.io/boxlambda/pico… #FPGA #RISCV

BoxLambda Devlog: An attempt at a PicoRV32-based Soft DMA Controller - Part 2 - Optimizations. epsilon537.github.io/boxlambda/pico… #RISCV #FPGA

BoxLambda Devlog: The Interconnect, Harvard Architecture, and Dual-Port RAM. epsilon537.github.io/boxlambda/inte… #RISCV #FPGA

BoxLambda Devlog: On USB HID, Keyboard LEDs, and device emulation. epsilon537.github.io/boxlambda/usb-… nand2mario Machdyne UG #FPGA #USB #RISCV #FORTH #j1

BoxLambda Devlog: SPI Flash Access, Boot, and Core. epsilon537.github.io/boxlambda/spi-… Zip CPU #FPGA #RISCV

I just pushed a devlog post about adding adding Hardware and Timer Interrupt support to BoxLambda: epsilon537.github.io/boxlambda/inte… #RISCV #FPGA

A new BoxLambda DevLog post: Keeping Time: RTCC and I2C epsilon537.github.io/boxlambda/i2c-… #FPGA Zip CPU

Finally, another BoxLambda post. Today's topic is Partial FPGA Reconfiguration: epsilon537.github.io/boxlambda/dfx/ Gateware is Software! #FPGA

No BoxLambda Blog post this time, but a big catch-up on Documentation: boxlambda.readthedocs.io/en/latest/ and various loose ends: github.com/epsilon537/box… All the gateware blocks are in place now 🥳🥳🥳

BoxLambda system tweaking in search of consistent instruction cycle counts: epsilon537.github.io/boxlambda/late…

In this post, I remove more functionality than I’m adding, and the BoxLambda SoC becomes a lot simpler and faster as a result. I’ll also briefly describe how the RISC-V GNU toolchain for BoxLambda is built. epsilon537.github.io/boxlambda/boxl… #RISCV #FPGA

In this post, I’ll explore ways to improve interrupt latency and jitter on the BoxLambda SoC. epsilon537.github.io/boxlambda/mini… #FPGA #RISCV

I just pushed a new BoxLambda release. The main additions are: - the BootLoader: boxlambda.readthedocs.io/en/latest/sw_c… - a complete Register Map: boxlambda.readthedocs.io/en/latest/regi… For a complete list of changes, please refer to the Release Notes: github.com/epsilon537/box… #FPGA #RISCV

epsilon537.github.io/boxlambda/sw-a… #fpga #forth #riscv

I started working towards the BoxLambda OS architecture I outlined in my previous post. I ported Mecrisp Quintus Forth and added a Forth-C FFI: epsilon537.github.io/boxlambda/fort… #forth #riscv #osdev #homebrewcomputer