Fred Chen (@drfrederickchen) 's Twitter Profile
Fred Chen

@drfrederickchen

Technology investigator

ID: 1529404402502471680

calendar_today25-05-2022 10:10:10

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To recover from the mistakes made in 1a and 1b, Samsung Electronics has focused all its efforts on mass-producing 1c DRAM ahead of SK hynix. It plans 1c production lines by the end of the year. biz.chosun.com/en/en-it/2025/…

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Per WSJ, NVIDIA's dominance in AI was a big recent contributor to Intel's troubles. Now, the question of whether Intel should work on its foundry or split it off has come up, in light of uncertainty over the appeal of its 18A process to external customers. wsj.com/tech/intel-ceo…

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EUV photoresist etch rate can be >10 nm/min in 30 mTorr (4 Pa) hydrogen plasma (think EUV-induced plasma). researchgate.net/publication/27…

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Hexapole illumination is popular for EUV lithography targeting DRAM storage node layers, but it is particularly vulnerable to stochastics. youtube.com/watch?v=9Y3Cue…

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Hard to believe N5 D0>1 on average (sometimes better, sometimes worse) at risk production: web.archive.org/web/2020052511…

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In the field of customized HBM base dies, customers, e.g., NVIDIA may begin to compete with their own suppliers, e.g., SK hynix, by designing their own. ctee.com.tw/news/202508167…

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The gap between DRAM bit line and storage node contact is getting smaller and smaller with successive generations, with only several nm for the D1b generation. No wonder SK hynix will apply the 4F² platform and 3D DRAM technology at 10 nm generation. news.skhynix.com/sk-hynix-prese…

The gap between DRAM bit line and storage node contact is getting smaller and smaller with successive generations, with only several nm for the D1b generation. No wonder SK hynix will apply the 4F² platform and 3D DRAM technology at 10 nm generation. news.skhynix.com/sk-hynix-prese…
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The shrinking gap between bit line and storage node contact (<10 nm) in 6F2 DRAM, and the shrinking gap (<9 nm) between word lines in 4F2 DRAM mean 3D DRAM would be the only possible option for higher density. semianalysis.com/2025/07/21/vls…

The shrinking gap between bit line and storage node contact (&lt;10 nm) in 6F2 DRAM, and the shrinking gap (&lt;9 nm) between word lines in 4F2 DRAM mean 3D DRAM would be the only possible option for higher density. semianalysis.com/2025/07/21/vls…
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The United States government will not seek a stake in TSMC, the company's CEO said Friday. WSJ quoted a U.S. govt official saying there were no plans to request shares from CHIPS Act recipients that increase their investments in the United States. focustaiwan.tw/business/20250…

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N5 EUV single exposure stochastic defect density rendered yield equivalent to 11 DUV exposures! open.substack.com/pub/frederickc…