I wrote a thing: "RISC-V Vector Extension for Integer Workloads: An Informal Gap Analysis" gist.github.com/camel-cdr/99a4… I'd love to get some opinions/feedback/ideas

RISC-V Vector Extension overview 0x80.pl/notesen/2024-1…

Here are some slightly tricky RVV mask patterns, with slight delay from 🐘

Here is a quick guide to C/C++ cross compilation for RISC-V on debian based systems:

SiFive X280 RVV benchmarks: camel-cdr.github.io/rvv-bench-resu… Civil was so nice to run my RVV benchmark on the SiFive X280 cores on the Tenstorrent Blackhole.

Geoff Langdale Jeff Smith It's obvious that a custom SIMD ISA can always beat or match a custom vector ISA because the set of SIMD ISA includes the set of vector ISAs. If you target an existing SIMD ISA vs an existing vector ISA, the vector ISA gives you more micro architectural flexibility.

Geoff Langdale Jeff Smith Fresh from ISC: "How to Make the Most out of SIMD on AArch64?" (ieeexplore.ieee.org/abstract/docum…) Covers different compiler tuning for autovectorization on aarch64.