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Die-to-die Interconnect Standards In Flux: Many features of UCIe 2.0 seen as “heavy” are optional, causing confusion. semiengineering.com/die-to-die-int… #UCIe #advancedpackaging #chiplets #interconnects #semiconductor

Latest news: Chip smuggling; AI export controls; Middle East AI deals; OSAT revenue up; AI PC memory chipsets; big fundings and buybacks; latest earnings; interconnects; AI accelerators; HBM4 bonder; SiC revenue and more. semiengineering.com/chip-industry-… #semiconductor #semiEDA

Chiplets offer a huge leap in semiconductor functionality and productivity, just like soft IP did 40 years ago, but a lot has to come together before that becomes reality. It takes an ecosystem, which is currently very rudimentary. semiengineering.com/development-fl… #chiplets

More Data, More Redundant Interconnects semiengineering.com/more-data-more… Circuits are being pushed harder and longer, particularly with AI, speeding up the aging of data paths. Photonics adds its own complications. #interconnects #semiconductor #AI #chiplets #advancedpackaging

Circuits are being pushed harder and longer, particularly with AI, speeding up the aging of data paths. Photonics adds its own complications. semiengineering.com/more-data-more… #semiconductor #interconnects #advancedpackaging

AI Accelerators Moving Out From Data Centers The explosion in AI data is driving chipmakers to look beyond a single planar SoC. SemiEngineering discussed the need for more computing & the expanding role of #chiplets w/7 industry experts semiengineering.com/ai-accelerator… #AI #accelerators

The intricacies of testing these complex devices, from maintaining contact with those pins even on warped substrates, to avoiding cross-talk, & monitoring how the coaxial sockets used to test these devices are functioning semiengineering.com/problems-in-te… #AIchips

New technical papers recently added to SemiEngineering’s library semiengineering.com/chip-industry-… #semiconductor #CFETs #RISCV #GPUs #hardwaresecurity #BEOL #chiplets #EUV #thermalmanagement MITRE Penn State News EPFL Intel Arizona State University IBM WPI National Institute of Standards and Technology Berkeley Lab Research

Cooling Chips Still A Top Challenge Heat pipes, lids, thermal interfaces, and micro-channel cooling help remove the heat generated by chips. semiengineering.com/cooling-chips-… #semiconductor #TIMs #heat #thermaldissipation #microchannelcooling #heatpipes

Latest news: China’s 3nm chip; imec’s next big push; hyper-dimensional AI chip; OpenAI’s $6.5B deal; Siemens new acquisition; France’s new OSAT; chip cooling; redundant interconnects; testing AI chips and more. semiengineering.com/chip-industry-… #semiconductor #semiEDA #3nm

News and insights from imec ITF World 2025: Jo De Boeck, chief strategy officer and EVP at imec, talks with SemiEngineering about system technology co-optimization and the intersection of technology and AI. semiengineering.com/inside-chips-p… #semiconductor

New materials play a pivotal role, but solving integration problems remains a challenge. semiengineering.com/advanced-packa… #semiconductor #advancedpackaging #heterogeneousintegration #CTE

Executive Outlook: Chiplets, 3D-ICs & AI Panel of experts at the ESD Alliance Executive Outlook meeting discuss chiplets and the challenges of moving to 3D-ICs. semiengineering.com/executive-outl… #semiEDA #3DIC #chiplets #semiconductor Ansys Siemens Digital Industries Software Keysight Cadence Synopsys

News: EDA export controls; ASE’s fan-out bridge; Synopsys-Ansys divest requirements; SIA Factbook; TSVs; earnings; TSMC’s new center; China’s legacy chips play; AMD’s buy; quantum-secure HW; executive outlook; co-packaged optics... semiengineering.com/chip-industry-… #semiconductor #semiEDA

Speeding Up Die-To-Die Interconnectivity Just adding more or thicker wires to a design isn’t sufficient with chiplets. semiengineering.com/speeding-up-di… #UCIe #chiplets #datamovement #semiEDA #interconnects #BoW

Special Report: Blazing fast data speeds come with significant manufacturing challenges. semiengineering.com/co-packaged-op… #CPO #copackagedoptics #datacenters #photonics

In the past, simulation was the only tool available for verification, but today there are many. Balancing the costs and rewards is not always easy. semiengineering.com/a-balanced-app… #semiEDA #verification #simulation