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After the full immersion CHISIC workshop of last week (ieee-cicc.org/chisic/) I am putting together a "single sentence" quantitative summary of where C2C connectivity is going from 2D to 2.5D to 3D: 1pJ/b (100s Gbps), 0.1pj/b (10s Gbps), 0.01pj/b (1s Gbps). Agreed?

This is very valuable IMHO also for developing HW RTL in systemverilog ... we should definitely try PULP Platform 😎

Very 'tutorial style', mostly focused on mainstream GPUs. But, it was fun to do it in Italian! 😏

People should listen to JH. He kmows what he is talking about. No half court tennis from him.

Dream team! 👍

Agreed.

😏

This is significantly pushing performance without giving up in efficiency with respect to CVA6. Quite a jump ahead for open-source linux-capable cores. Great collaboration with industry partners. Fully open-source of course!

Look at what we can do with bioGAP! 😎

A video is worth 10K words... 👍

Cool!

Not to be missed! PULP Platform at the RISC-V International summit!

Highly recommended! Good job by Sergio!

🤯

Sooo cool! The Basilisk SoC, End-to-end (design, EDA tools, PDK) linux-booting open source silicon by PULP Platform goes to hot chips! 😎 Demo warning! 🤩

👍

Writing this paper was great fun, and quite some work... 🙏 Marian for the discipline ;-) I hope it will help understand how to design accelerators! By the way, there is a typo in one formula... cookie point if someone finds it before it's officially corrected 😏

Here is it, on arxiv!

have been waiting for quite some time to talk about FlatAttention. Now finally the genie is out of the bottle... 🚀 Architecture+dataflow which IMHO will be dominating the next generation of scaled ML systems: Powerful on-chip collectives and multicast, and fat compute tiles.

I promised to PULP Platform to never do supercalar (too much hard engineering vs. research 🙄). However it was worth it. We need high quality open source cores, with industry support , to climb the performance ladder at high energy efficiency. The team did it! 👍