Check out the latest article in my newsletter: EDAgraffiti Returns linkedin.com/pulse/edagraff… via LinkedIn

I will be in Boston/Cambridge MA next week. If you're an AI chip company in Boston that I haven't already set up a meeting with, please drop me a line.

AD & #GenAI give the semi engineering community training & inference processing nightmares because current algorithmic HW is not able to accelerate execution. VSORA & 2 classes of algorithmic accelerators for AD applications/GenAI acceleration can! tinyurl.com/mrx5dzkh

DVCon Europe Wednesday program includes the topical panel "All #ai All the time" with a great moderator and terrific set of panelists. Join us and bring questions. Paul Dempsey Jean-Marie Brunet Siemens Digital Industries Software Michaela Blott AMD Lu Dai Accellera Qualcomm

We are excited to announce RISC-V Summit Europe 2024, the event connecting the European movers and shakers that are building the future of innovation on #RISCV. See you in Munich, Germany from June 24-28! hubs.la/Q028S4pR0 #RISCVeverywhere #RISCVSummitEurope

The #IndustrialMetaverse will revolutionize design and collaboration in the #manufacturing sector. We're proud to be recognized as "a clear leader" in this area. Read the 2023 PAC RADAR Report “Open Digital Platforms for the Industrial World” for more: sie.ag/4ebvER

As Jean-Marie Brunet told SemiWiki Dan Nenni, Siemens hardware-assisted verification has a unique vantage point, practicing the same thing as its customers. tinyurl.com/d5ws2rn8

Hardware-assisted verification is becoming an enabler for the emerging ecosystem based on its ability to run many cycles of software-driven validation, notes Jean-Marie Brunet, VP/GM of the Siemens HAV group. #semieda #verifcation #semiconductor #HAV eetimes.eu/hardware-assis…

Read EE Times Europe’s article to learn why #RISCV is an exciting development for hardware-assisted verification vendors and how the RISC-V ecosystem can build a rich verification environment that designers can trust: hubs.la/Q02bhd0z0 #RISCVeverywhere

Lauro Rizzatti's 11 Myths Abt GenAI breaks GenAI misunderstandings 4 Electronic Design VSORA Jotunn is an all-in-1 single-chip for massive a Genai performance jump in inferencing processing accelerating the proliferation of low-cost & power GenAI. tinyurl.com/mr258nk7

Lauro Rizzatti VSORA -- what now that SW is eating HW. His take? The semi industry has an opportunity to challenge the status quo w/improved hardware infrastructure built on an innovative processing architecture lnkd.in/guNcBQHD

Congratulations to Edwards Vacuum for receiving the 2023 SEMI Industry Leader in #Diversity and #Inclusion Award! The award recognizes European chip companies that exhibit outstanding leadership and make strategic contributions to fostering #DEI. 👉 bit.ly/4aqulQT

Happy Holidays to everyone! We had a blast this year. We hope the next year brings happiness, peace and joy to everyone! To many more years of #formalverification building proofs of bug absence! #semiconductors #diversityandinclusion #2023year

The Coffee Chat Series was created with you in mind, get the details on our programs, events, and find the support you need. Join us, stay connected and ask away; we're here to help! hubs.la/Q02cQpt-0

Are you passionate about RISC-V and want to expand its reach in your local community? We’re on the lookout for Advocates and Ambassadors around the world! Check out which one you qualify for under the community tab on: hubs.la/Q02dvhC30 #RISCVambassadors #RISCVadvocates

On Thursday, Jan. 25, join fellow RISC-V enthusiasts for our in-person RISC-V Munich meetup! Register today to learn more about what’s happening in the global #RISCV community: hubs.la/Q02gRx-S0 #RISCVeverywhere

Investor Luc Burgun is a huge @VSORA fan. Today's post on SemiWiki.com explains why. #jotunn #Tyr #GPU #genai #ai #semiconductortechnology #AD #llms semiwiki.com/ceo-interviews…