New FPGA! I want to try a soft PCIe bridge on this one. I can do 2 PL and 1 PS PCIe core. Also maybe try an open source soft core that connects directly to the transceivers.

openFPGALoader now support basic PDI programming for AMD Spartan Ultrascale+ FPGAs! This is just basic functionality to get started. What other features do you need for PDI support? github.com/trabucayre/ope…

Working on a video about the FPGA accelerator box that I'm building, planning to post it tomorrow. In the meantime, here are some 16 GT/s diff pairs, from said project.

Going live next week to show the DisplayPort interface on the Agilex 5 FPGA. I’ll walk through the IP example, trace TX→RX data flow, and build a small setup to tweak the video stream. Thanks to Altera for supporting this demo! youtube.com/live/kMHdRUPAN…

In two weeks, I’ll try rapid FPGA prototyping on the AMD Spartan UltraScale+ with MicroBlaze V. 🛰️ GPS (Serial) 📡 LoRa (SPI) 📈 Accelerometer (I²C) youtube.com/live/EgNPFLsXK…

Does anyone else use xrdp with docker? It worked great getting quartus to actually work on the Altera docker image. I want to publish docker images for all the FPGA tools :).

I modified the official Altera Docker image to include xRDP, RISCFREE tools, and a ready-to-build setup for the Agilex 5 FPGA DisplayPort example. Added easy build instructions so anyone can follow along with tomorrow’s livestream. github.com/AEW2015/altera…

Its amazing how fast a little RP2040 can go! With a Parrallel bus of 8 bits you can easily support 40 MB/s bus to the AMD FPGA. Can you use a RP2040 to do a SMI-like memory interface to the co-FPGA?

My next Altera FPGA AI video will show how to make simple ONNX models to test the FPGA AI Suite streaming interfaces on the Agilex 5, checking control and data flow before running a full neural network. youtube.com/live/-re3mXWRL…

Weekend FPGA project time! Exploring the Altera Agilex 5 PCIe PIO example using a Python driver and a Raspberry Pi CM4 host. Drop by the stream and hang out! youtube.com/live/bD4XTlwnN…

This is a big cable mess but got the White Rabbit (nanosecond-level time synchronization) sorta working! I’m using two baseboards, one with an Acorn acting as a clock reference and the other with a Litex M2SDR acting as a client. I’m using a direct attach cable instead of a

The AMD MicroBlaze V (RISC-V) can handle AXI-Stream packets with dedicated instructions. The soft processor can do register direct to an FPGA accelerator. Gonna try a few simple HLS accelerators and see how well it works.

Weekend project: Using the MicroBlaze V RISC-V AXI-Stream, I want to try talking to the PIOs on the RP2040. Going to prototype the link and see what kind of speed I can get. Feel free to drop by! youtube.com/live/a7hFD_DbA…

You mean I can get this working on AMD ZYNQ & Versal FPGAs?

This is a great video on all the fun behind designing a soft RISC-V processor from scratch. youtu.be/85-gHOcqhEg?si…

Here is the CoreScore for AMD’s Spartan UltraScale+ on the SCU35 dev board ⇒ 83 SERV RISC-V cores! Awesome, easy-to-use benchmark from Olof Kindgren . I’ll have the basic PR up soon.

Got simple Vitis HLS blocks working with the MicroBlaze RISC-V processor using the AXI4-Stream FSL features. Thinking about trying some Advent of Code 2024 puzzles as fun accelerator challenges next!

Weekend FPGA side quest! Gonna get Altera Nios-V talking to the AD9364 over SPI and fire up the LVDS test modes. youtube.com/live/BfQpUtdCs…