Andrew Elbert Wilson (@fpga_zealot) 's Twitter Profile
Andrew Elbert Wilson

@fpga_zealot

ID: 751503987380105216

linkhttps://discord.gg/k9BYa9VrR3 calendar_today08-07-2016 19:51:27

708 Tweet

1,1K Followers

395 Following

Andrew Elbert Wilson (@fpga_zealot) 's Twitter Profile Photo

New FPGA! I want to try a soft PCIe bridge on this one. I can do 2 PL and 1 PS PCIe core. Also maybe try an open source soft core that connects directly to the transceivers.

New FPGA!  I want to try a soft PCIe bridge on this one.  I can do 2 PL and 1 PS PCIe core.  Also maybe try an open source soft core that connects directly to the transceivers.
Andrew Elbert Wilson (@fpga_zealot) 's Twitter Profile Photo

openFPGALoader now support basic PDI programming for AMD Spartan Ultrascale+ FPGAs! This is just basic functionality to get started. What other features do you need for PDI support? github.com/trabucayre/ope…

openFPGALoader now support basic PDI programming for AMD Spartan Ultrascale+ FPGAs!  This is just basic functionality to get started.  What other features do you need for PDI support?
github.com/trabucayre/ope…
Peter Schmidt-Nielsen (@ptrschmdtnlsn) 's Twitter Profile Photo

Working on a video about the FPGA accelerator box that I'm building, planning to post it tomorrow. In the meantime, here are some 16 GT/s diff pairs, from said project.

Working on a video about the FPGA accelerator box that I'm building, planning to post it tomorrow. In the meantime, here are some 16 GT/s diff pairs, from said project.
Andrew Elbert Wilson (@fpga_zealot) 's Twitter Profile Photo

Going live next week to show the DisplayPort interface on the Agilex 5 FPGA. I’ll walk through the IP example, trace TX→RX data flow, and build a small setup to tweak the video stream. Thanks to Altera for supporting this demo! youtube.com/live/kMHdRUPAN…

Andrew Elbert Wilson (@fpga_zealot) 's Twitter Profile Photo

In two weeks, I’ll try rapid FPGA prototyping on the AMD Spartan UltraScale+ with MicroBlaze V. 🛰️ GPS (Serial) 📡 LoRa (SPI) 📈 Accelerometer (I²C) youtube.com/live/EgNPFLsXK…

Andrew Elbert Wilson (@fpga_zealot) 's Twitter Profile Photo

Does anyone else use xrdp with docker? It worked great getting quartus to actually work on the Altera docker image. I want to publish docker images for all the FPGA tools :).

Does anyone else use xrdp with docker?  It worked great getting quartus to actually work on the Altera docker image.  I want to publish docker images for all the FPGA tools :).
Andrew Elbert Wilson (@fpga_zealot) 's Twitter Profile Photo

I modified the official Altera Docker image to include xRDP, RISCFREE tools, and a ready-to-build setup for the Agilex 5 FPGA DisplayPort example. Added easy build instructions so anyone can follow along with tomorrow’s livestream. github.com/AEW2015/altera…

Andrew Elbert Wilson (@fpga_zealot) 's Twitter Profile Photo

Its amazing how fast a little RP2040 can go! With a Parrallel bus of 8 bits you can easily support 40 MB/s bus to the AMD FPGA. Can you use a RP2040 to do a SMI-like memory interface to the co-FPGA?

Its amazing how fast a little RP2040 can go!  With a Parrallel bus of 8 bits you can easily support 40 MB/s bus to the AMD FPGA.  Can you use a RP2040 to do a SMI-like memory interface to the co-FPGA?
Andrew Elbert Wilson (@fpga_zealot) 's Twitter Profile Photo

My next Altera FPGA AI video will show how to make simple ONNX models to test the FPGA AI Suite streaming interfaces on the Agilex 5, checking control and data flow before running a full neural network. youtube.com/live/-re3mXWRL…

Andrew Elbert Wilson (@fpga_zealot) 's Twitter Profile Photo

Weekend FPGA project time! Exploring the Altera Agilex 5 PCIe PIO example using a Python driver and a Raspberry Pi CM4 host. Drop by the stream and hang out! youtube.com/live/bD4XTlwnN…

Luigi Cruz (@luigifcruz) 's Twitter Profile Photo

This is a big cable mess but got the White Rabbit (nanosecond-level time synchronization) sorta working! I’m using two baseboards, one with an Acorn acting as a clock reference and the other with a Litex M2SDR acting as a client. I’m using a direct attach cable instead of a

This is a big cable mess but got the White Rabbit (nanosecond-level time synchronization) sorta working!

I’m using two baseboards, one with an Acorn acting as a clock reference and the other with a Litex M2SDR acting as a client. I’m using a direct attach cable instead of a
Andrew Elbert Wilson (@fpga_zealot) 's Twitter Profile Photo

The AMD MicroBlaze V (RISC-V) can handle AXI-Stream packets with dedicated instructions. The soft processor can do register direct to an FPGA accelerator. Gonna try a few simple HLS accelerators and see how well it works.

The AMD MicroBlaze V (RISC-V) can handle AXI-Stream packets with dedicated instructions.  The soft processor can do register direct to an FPGA accelerator.  Gonna try a few simple HLS accelerators and see how well it works.
Andrew Elbert Wilson (@fpga_zealot) 's Twitter Profile Photo

Weekend project: Using the MicroBlaze V RISC-V AXI-Stream, I want to try talking to the PIOs on the RP2040. Going to prototype the link and see what kind of speed I can get. Feel free to drop by! youtube.com/live/a7hFD_DbA…

Weekend project: Using the MicroBlaze V RISC-V AXI-Stream, I want to try talking to the PIOs on the RP2040. Going to prototype the link and see what kind of speed I can get. Feel free to drop by!
youtube.com/live/a7hFD_DbA…
Andrew Elbert Wilson (@fpga_zealot) 's Twitter Profile Photo

Here is the CoreScore for AMD’s Spartan UltraScale+ on the SCU35 dev board ⇒ 83 SERV RISC-V cores! Awesome, easy-to-use benchmark from Olof Kindgren . I’ll have the basic PR up soon.

Here is the CoreScore for AMD’s Spartan UltraScale+ on the SCU35 dev board ⇒ 83 SERV RISC-V cores!
Awesome, easy-to-use benchmark from <a href="/OlofKindgren/">Olof Kindgren</a> .  I’ll have the basic PR up soon.
Andrew Elbert Wilson (@fpga_zealot) 's Twitter Profile Photo

Got simple Vitis HLS blocks working with the MicroBlaze RISC-V processor using the AXI4-Stream FSL features. Thinking about trying some Advent of Code 2024 puzzles as fun accelerator challenges next!

Got simple Vitis HLS blocks working with the MicroBlaze RISC-V processor using the AXI4-Stream FSL features. Thinking about trying some Advent of Code 2024 puzzles as fun accelerator challenges next!
Andrew Elbert Wilson (@fpga_zealot) 's Twitter Profile Photo

Weekend FPGA side quest! Gonna get Altera Nios-V talking to the AD9364 over SPI and fire up the LVDS test modes. youtube.com/live/BfQpUtdCs…